The present invention relates in general to forming transistors in integrated circuits (ICs). More specifically, the present invention relates to improved systems, fabrication methodologies and resulting structures for vertical field effect transistors (FETs) that include relatively high aspect ratio structures, are self-aligned, have merged gates and include sufficient area for placement of a merged gate contact.
Semiconductor devices are typically formed using active regions of a wafer. In an IC having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material.
One type of MOSFET is a non-planar FET known generally as a vertical FET. In order to decrease gate pitch (i.e., the center-to-center distance between adjacent gate structures) and increase device density on the wafer, the aspect ratios of the channel region and the gate region of a typical vertical FET device are high. In other words, the channel and gate regions are each much taller than they are wide. However, overlay errors in known lithography fabrication techniques impose lower limits on gate thickness, thereby making it a challenge to fabricate vertical FET structures having the desired high aspect ratios.